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[Windows DevelopViterbiFPGA

Description:
Platform: | Size: 3784704 | Author: 鲁东旭 | Hits:

[Other Embeded programSKRETD(low_power)

Description: 硕士论文,viterbi译码器的低功耗设计,最后附带源码,VHDL-master's thesis, Viterbi Decoder low-power design, the final collateral source, VHDL
Platform: | Size: 380928 | Author: xialu | Hits:

[Communication-Mobileviterbi213

Description:
Platform: | Size: 3343360 | Author: 潘 应 云 | Hits:

[Program docViterbi

Description: 三篇关于Viterbi FPGA编译码器的优化设计文档: 1、Viterbi译码器的FPGA设计实现与优化.pdf 2、Viterbi译码器的低功耗设计.pdf 3、基于FPGA的高速并行Viterbi译码器的设计与实现.pdf-3 on the Viterbi FPGA optimization codecs design documents: 1, Viterbi decoder FPGA Design Implementation and Optimization. Pdf2, Viterbi decoder, low-power design. Pdf3, high-speed FPGA-based parallel Viterbi decoder Design and Implementation. pdf
Platform: | Size: 451584 | Author: helei_zju | Hits:

[VHDL-FPGA-Verilogviterbi

Description: 介绍了viterbi译码器的编解码器的设计,包括decoder.v,encoder.v.control.v,ram.v等,压缩 包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Platform: | Size: 62464 | Author: yaoyongshi | Hits:

[Program docviterbi

Description: 基于XilinxFPGA的高速Viterbi回溯译码器-Based on retrospective XilinxFPGA high-speed Viterbi decoder
Platform: | Size: 198656 | Author: mediative | Hits:

[Program docviterbi

Description: 维特比译码器的asic设计的相关论文-Viterbi Decoder asic design related articles
Platform: | Size: 277504 | Author: mediative | Hits:

[VHDL-FPGA-VerilogViterbi_IP

Description: viterbi译码器的IP核,可以直接编译使用-viterbi decoder IP core, the compiler can directly use
Platform: | Size: 75776 | Author: nianln | Hits:

[VHDL-FPGA-Veriloghusw

Description: 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
Platform: | Size: 1024 | Author: hsw0320 | Hits:

[VHDL-FPGA-VerilogViterbi

Description: Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
Platform: | Size: 8192 | Author: 蔡敏 | Hits:

[Communication-Mobileurn_nbn_se_liu_diva-6949-1__fulltext

Description: Viterbi decoder algorithm
Platform: | Size: 562176 | Author: Hossam Ahmed | Hits:

[VHDL-FPGA-Verilogviterbi

Description: verilog程序,实现了(2,1,4)卷积码编码,和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Platform: | Size: 3072 | Author: xiongherui | Hits:

[VHDL-FPGA-VerilogViterbi_decoder

Description: Viterbi译码器的编解码器的设计 用Verilog实现-Viterbi decoder。Verilog
Platform: | Size: 64512 | Author: 李风飞 | Hits:

[Software Engineeringvit_dec

Description: viterbi decoder implementation
Platform: | Size: 5120 | Author: rocky mehta | Hits:

[VHDL-FPGA-Verilogviterbi

Description: viterbi decoder with convolutional encoder
Platform: | Size: 1389568 | Author: phani | Hits:

[VHDL-FPGA-Verilogreinformationregardingapplicationfee

Description: paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that include s Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format -paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format
Platform: | Size: 431104 | Author: awa | Hits:

[VHDL-FPGA-Verilogviterbi_binary_hard_c

Description: vhdl code for viterbi decoder
Platform: | Size: 4096 | Author: anjali | Hits:

[VHDL-FPGA-Verilogviterbi

Description: verilog code for viterbi encoder and decoder
Platform: | Size: 13312 | Author: kamran | Hits:

[VHDL-FPGA-Verilogviterbi.decoder

Description:
Platform: | Size: 11264 | Author: thang | Hits:

[VHDL-FPGA-VerilogVD-vhdl-Code

Description: this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
Platform: | Size: 7168 | Author: shishir | Hits:
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